High Performance and Area-Efficient Circuit-Switched Network on Chip Design

High performance and area-efficient circuitswitched on chip network using 4x4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18¿m process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.