Degradation Mechanisms in CMOS Power Amplifiers Subject to Radio-Frequency Stress and Comparison to the DC Case

An in-depth study of the degradation dynamics in CMOS power amplifiers is presented. The transistor was operated at 1.9 GHz under real-world load and power conditions. Threshold voltage and sub-threshold slope were monitored as a measure of the device degradation versus stress time. Experimental evidence is provided, which demonstrates that damage severity strongly depends on the features of drain voltage and current waveforms, rather than on average dissipated power. The results of RF stress tests are compared to dc hot carrier and Fowler-Nordheim experiments. Large discrepancies are found between measurements and the quasi-static model.