Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

Author

Boselli, Gianluca ; Vassilev, Vesselin ; Duvvury, Charvaka

Author_Institution

Silicon Technol. Dev., Texas Instruments, Dallas, TX

fYear

2007

fDate

15-19 April 2007

Firstpage

342

Lastpage

347

Abstract

In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I _T2~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; 65 nm; CMOS technology; drain-extended nMOS transistors; electrostatic discharge protection; substrate biasing; CMOS technology; Diodes; Electrostatic discharge; Implants; MOS devices; MOSFETs; Protection; Robustness; Thyristors; Voltage; DEnMOS; ESD; USB2.0; state-of-art CMOS technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability physics symposium, 2007. proceedings. 45th annual. ieee international

Conference_Location

Phoenix, AZ

Print_ISBN

1-4244-0919-5

Electronic_ISBN

1-4244-0919-5

Type

conf

DOI

10.1109/RELPHY.2007.369913

Filename

4227654

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2783303