Architectural considerations for a M88000 superscalar RISC processor

With current RISC performances being matched or even surpassed by CISC processors like the MC68040, the future direction for RISC lies in the concept of multiple execution machines where multiple instructions are executed per clock. Although, the basic tenets of RISC design of fixed instruction length, regular decoding, and non-destructive data operations offer a big advantage over CISC architectures in implementing such designs, there are still several problems to overcome. The ease of solution is frequently dependent on architectural decisions made early in its implementation. The author examines the Motorola MC88100 processor architecture and explains why certain key features were implemented and their benefit to later generations like the forthcoming MC88110 in breaking the one instruction per clock barrier. Topics discussed include data dependency between instructions and some suggested optimising techniques, pipeline control and its importance, condition evaluation, and a brief overview of the MC88110