Designing RISCs using PLDs

One of the concepts which originally spurred development of the RISC philosophy was simplicity. That through simplified digital designs higher execution speed can be achieved by reduced propagation delays and direct instruction decoding. One side effect of this simplicity concept was the `small´ number of logic gates required to implement the new designs enabling existing ASICs and gate arrays to be used rather than seeking to reduce geometries further to obtain more transistors on the silicon chip. There is now beginning to be a convergence between the number of gates required to implement the most simple RISC designs and the number of gates available on the cheaper Programmable Logic Devices (PLD) such as the MACH110, enabling much more practical experimentation. Many of these devices are also erasable enabling many iterations of design and test to be performed in a short time