DocumentCode
2787284
Title
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling
Author
Lee, Jungseob ; Sathisha, Vijay ; Schulte, Michael ; Compton, Katherine ; Kim, Nam Sung
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA
fYear
2011
fDate
10-14 Oct. 2011
Firstpage
111
Lastpage
120
Abstract
State-of-the-art graphic processing units (GPUs) can offer very high computational throughput for highly parallel applications using hundreds of integrated cores. In general, the peak throughput of a GPU is proportional to the product of the number of cores and their frequency. However, the product is often limited by a power constraint. Although the throughput can be increased with more cores for some applications, it cannot for others because parallelism of applications and/or bandwidth of on-chip interconnects/caches and off-chip memory are limited. In this paper, first, we demonstrate that adjusting the number of operating cores and the voltage/frequency of cores and/or on-chip interconnects/caches for different applications can improve the throughput of GPUs under a power constraint. Second, we show that dynamically scaling the number of operating cores and the voltages/frequencies of both cores and on-chip interconnects/caches at runtime can improve the throughput of application even further. Our experimental results show that a GPU adopting our runtime dynamic voltage/frequency and core scaling technique can provide up to 38% (and nearly 20% on average) higher throughput than the baseline GPU under the same power constraint.
Keywords
cache storage; graphics processing units; parallel processing; power aware computing; core scaling; dynamic voltage-frequency scaling; graphic processing units; off-chip memory; on-chip caches; on-chip interconnects; parallel applications; power-constrained GPU; throughput improvement; Bandwidth; Frequency domain analysis; Graphics processing unit; Memory management; Power demand; System-on-a-chip; Throughput; GPU; core scaling; dynamic voltage; frequency; power constraint; throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on
Conference_Location
Galveston, TX
ISSN
1089-795X
Print_ISBN
978-1-4577-1794-9
Type
conf
DOI
10.1109/PACT.2011.17
Filename
6113793
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