A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp

A 10b 120MS/s pipeline ADC is implemented in a 45nm CMOS process. Three-stage amplifiers based on RNMC and multi-path zero cancellation techniques are employed in the SHA and two MDACs. A re-configurable three-stage switched amplifier is shared between adjacent MDACs without series switches and memory effects. A charge redistributed input sampling network properly handles single-ended or differential SHA inputs. The prototype ADC with an active die area of 0.58mm² consumes 61.6mW at 120MS/s and 1.1V. The measured DNL and INL are within 0.44LSB and 0.75LSB, respectively. At a clock of 120MHz with a 1.2Vpp 4.2MHz sinusoidal input, the measured SNDR and SFDR are 55.1dB and 70.0dB, respectively.