DocumentCode
2788863
Title
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
Author
Rana, V. ; Santambrogio, M. ; Sciuto, D. ; Kettelhoit, B. ; Koester, M. ; Porrmann, M. ; Ruckert, U.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano
fYear
2007
fDate
26-30 March 2007
Firstpage
1
Lastpage
8
Abstract
Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a multi-FPGA clustered architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-cores into the system at run-time. For the resource management and communication management we have implemented a Linux operating system on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration.
Keywords
Linux; embedded systems; field programmable gate arrays; microprocessor chips; reconfigurable architectures; Linux operating system; communication management; embedded processor; multi FPGA clustered architecture; partial dynamic reconfiguration hardware; resource management; user-defined IP-cores; Communication system control; Computer architecture; Control systems; Field programmable gate arrays; Hardware; Linux; Logic arrays; Operating systems; Resource management; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
Conference_Location
Rome
Print_ISBN
1-4244-0909-8
Type
conf
DOI
10.1109/IPDPS.2007.370363
Filename
4228091
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