• DocumentCode
    2790580
  • Title

    Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques

  • Author

    Lv, Jinpeng ; Kalla, Priyank ; Enescu, Florian

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • fYear
    2011
  • fDate
    9-11 Nov. 2011
  • Firstpage
    136
  • Lastpage
    143
  • Abstract
    Galois field computations abound in many applications, such as in cryptography, error correction codes, signal processing, among many others. Multiplication usually lies at the core of such Galois field computations, and is one of the most complex operations. Hardware implementations of such multipliers become very expensive. Therefore, there have been efforts to reduce the design complexity by decomposing the Galois field GF(2k) as GF ((2m)n) where k = m × n. Such a decomposition introduces a hierarchical abstraction - lifting the ground field from GF (2) (bit-level) to GF (2m) (word-level) - thus simplifying the design. This paper addresses the formal verification problem of such multipliers designed over GF ((2m)n), using a computer algebra and algebraic geometry based approach. To prove that the composite field multiplier implementation matches the original specification, we hierarchically formulate the verification problem using the Hilbert´s Nullstellensatz over Galois Fields. A Gröbner basis engine is employed as the underlying computational framework. Experiments are performed with various variable/term orders to demonstrate the efficacy of our approach. We can verify the correctness of upto 1024bit multipliers, whereas SAT/SMT-based approaches are in-feasible.
  • Keywords
    Galois fields; formal verification; symbol manipulation; GF ((2m)n); algebraic geometry; complex operations; composite Galois field multiplier verification; computational framework; computer algebra techniques; cryptography; error correction codes; formal verification problem; signal processing; Computers; Galois fields; Integrated circuit modeling; Mathematical model; Polynomials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International
  • Conference_Location
    Napa Valley, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4577-1744-4
  • Type

    conf

  • DOI
    10.1109/HLDVT.2011.6113989
  • Filename
    6113989