The mixed serial/parallel approach to VLSI search processors

Discusses a design methodology for VLSI search processors whereby most of the processing elements of previous designs are replaced with high-speed shift registers. Such an approach results in a significant cost reduction while maintaining a reasonable suboptimal processing speed for databases of practical interest. As an added benefit, the proposed designs offer considerable flexibility in the handling of variable-length and very long records. Such records are impossible to handle or lead to intolerable performance penalties with fixed-format designs. A key to the proposed architecture is the coupling of high-speed shift registers with systolic string comparators that can operate at extremely high clock rates. The speed/cost tradeoffs provided by various architectural features of the proposed system are discussed and its performance is compared to those of certain theoretically optimal, but currently unrealizable hardware-intensive architectures