Equalizer design and performance trade-offs in ADC-based serial links

To address the increasing demand but potential power/area penalties of implementing ADC-based high-speed serial receivers, this paper analyzes the performance benefit of using non-uniform quantization and describes a way of determining the optimal set of ADC quantization thresholds. In contrast to common wisdom, the ADC thresholds for the minimum bit-error rate (BER) can be very different from those for the minimum quantization errors, especially with limited ADC resolution. It is recognized that the loop-unrolling DFE receiver and ADC-based DFE receiver are functionally equivalent and thus can share some design principles. The proposed reduced-slicer partial-response DFE (RS-PRDFE) receiver leverages this fact and achieves the BER of a 3~4-bit uniform ADC only with 4 data slicers. However, performing linear equalization (LE) in digital domain in addition to the DFE may incur severe performance penalty if the ADC resolution is kept coarse. Therefore, for practical implementations, it is more reasonable to realize the LE in analog domain. Analyses based on the measured results with 3" and 10.6" backplane channels support this claim.