DocumentCode
2791319
Title
Decomposing refinement proofs using assume-guarantee reasoning
Author
Henzinger, T.A. ; Qadeer, S. ; Rajamani, S.K.
Author_Institution
California Univ., Berkeley, CA, USA
fYear
2000
fDate
5-9 Nov. 2000
Firstpage
245
Lastpage
252
Abstract
Model-checking algorithms can be used to verify, formally and automatically, if a low-level description of a design conforms with a high-level description. However, for designs with very large state spaces, prior to the application of an algorithm, the refinement-checking task needs to be decomposed into subtasks of manageable complexity. It is natural to decompose the task following the component structure of the design. However, an individual component often does not satisfy its requirements unless the component is put into the right context, which constrains the inputs to the component. Thus, in order to verify each component individually, we need to make assumptions about its inputs, which are provided by the other components of the design. This reasoning is circular: component A is verified under the assumption that context B behaves correctly, and symmetrically, B is verified assuming the correctness of A. The assume-guarantee paradigm provides a systematic theory and methodology for ensuring the soundness of the circular style of postulating and discharging assumptions in component-based reasoning. We give a tutorial introduction to the assume-guarantee paradigm for decomposing refinement-checking tasks. To illustrate the method, we step in detail through the formal verification of a processor pipeline against an instruction set architecture. In this example, the verification of a three-stage pipeline is broken up into three subtasks, one for each stage of the pipeline.
Keywords
computational complexity; formal verification; high level synthesis; inference mechanisms; assume-guarantee paradigm; assume-guarantee reasoning; formal verification; instruction set architecture; model-checking algorithms; refinement proofs; three-stage pipeline; Algorithm design and analysis; Formal verification; Graphics; Hardware; Information technology; Pipelines; Protocols; Signal processing; Silicon; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-6445-7
Type
conf
DOI
10.1109/ICCAD.2000.896481
Filename
896481
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