Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor

As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and electronic design automation (EDA) industries, which may cause significantly increased mismatch between modeled and actual silicon behavior, and even IC failure in field. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch and perform in-field measurements. This paper presents a novel standard-cell-based sensor for reliability analysis of digital ICs (called Radic), in order to better understand the characteristics of gate, functional path aging and process variations´ impact on timing performance, and perform in-field aging measurements. The Radic sensor has been fabricated on two floating gate Freescale SoCs in very advanced technology. The measurement results demonstrate that the resolution can be better than 0.1 ps, and the accuracy is kept throughout aging/process variation. Additionally, a built-in aging adaption system based on Radic sensor is proposed to perform in-field aging adaption. Simulation results verify that, comparing with designs with fixed aging guardband, the proposed aging adaption system releases 80% of aging timing margin, saves silicon area by 1.02%-3.16% at most targeting frequencies, and prevents aging induced failure.