20 V LDMOS optimized for high drain current condition. Which is better, n-epi or p-epi?

Author

Kinoshita, Kozo ; Kawaguchi, Yusuke ; Sano, Takeshi ; Nakagawa, Akio

Author_Institution

Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

fYear

1999

fDate

1999

Firstpage

59

Lastpage

62

Abstract

This paper discusses whether n-epi or p-epi substrates are better for 20 V range LDMOSFETs. We present four optimized 20 V LDMOSFETs and compare them. The best compromise is the LDMOS on n-epi with a high dose n-implant layer which achieves a sufficiently low on-resistance of 17.2 mΩ·mm² and a high static breakdown voltage of 24.0 V without breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 24.5 V

Keywords

doping profiles; electric current; ion implantation; optimisation; power MOSFET; semiconductor device breakdown; semiconductor device testing; semiconductor epitaxial layers; substrates; 20 V; 24 V; 24.5 V; 5 V; LDMOS optimization; Si; breakdown voltage degradation; device on-state breakdown voltage; drain current; drain current flow; gate voltage; high dose n-implant layer; n-epi substrates; on-resistance; optimized LDMOSFETs; p-epi substrates; static breakdown voltage; Application software; Bipolar transistors; Breakdown voltage; Computer applications; Degradation; Design optimization; Implants; MOSFETs; Petroleum; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on

Conference_Location

Toronto, Ont.

ISSN

1063-6854

Print_ISBN

0-7803-5290-4

Type

conf

DOI

10.1109/ISPSD.1999.764049

Filename

764049