A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

Author

Kim, Tae-hyoung ; Sung, Jun-jey ; Kim, Soo-hwan ; Joo, Woong ; You, Seung-Bin ; Kim, Suki

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul, South Korea

fYear

2000

fDate

2000

Firstpage

57

Lastpage

60

Abstract

This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. To reduce the nonlinear errors in the sample-and-holder (S/H), a charge-pump circuit is used. By using a wide range error correction scheme, the relaxed design of comparators is possible. The ADC was designed using a 0.25 μm 1-poly 5-metal CMOS process. It consumes 62 mW at 40 Msamples/s. The INL/DNL is less than 0.5 LSB/0.4 LSB by MATLAB presimulation

Keywords

CMOS integrated circuits; analogue-digital conversion; cascade networks; error correction; interpolation; 0.25 micron; 1-poly 5-metal CMOS process; 10 bit; 62 mW; A/D converter; CMOS ADC; analog-to-digital converter; cascading architecture; charge-pump circuit; comparators reduction; folding/interpolating ADC; input signal bandwidth; nonlinear errors; power consumption reduction; sample/holder; wide range error correction; Bandwidth; Capacitors; Charge pumps; Circuits; Clocks; Samarium; Sampling methods; Signal design; Signal generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896907

Filename

896907