High performance data acquisition systems

The author describes the specific considerations which apply in respect of achieving a viable architecture for enabling the proper acquisition of data with frequency components in excess of 100 KHz, using hardware designed to interface with the PC bus. Allied to the above are issues relating to aspects of triggering techniques aimed at maximising the capture of relevant data, and thereby minimising the need for complex data reduction algorithms operating on an excess of raw data. The theme is developed to describe means of acquiring data in an essentially simultaneous manner from multiple channels. Ways are described in which a large subset of the above techniques and circuitry is applied to another form of high performance data acquisition, in this case characterised by high (16-bit) resolution at still moderately high speed (50-KHz)