Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in at-speed delay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results for a set of industrial circuits show that the proposed method, on average, reduces test data volume by a factor 2.7, switching activity during scan shift by a factor of 5 and peak switching activity during test response capture by a factor of 2.