Test Compression Based on Lossy Image Encoding

Test compression / decompression is one of effective methods for testing today´s VLSI. In this paper, we discuss test compression with image compression algorithms, e.g., JPEG algorithm. Image compression algorithms can not only achieve considerably high compression but also require no additional decompression circuity on a chip under test if the chip includes image decoders. Moreover, we propose a method for generating seeds (or compressed test data) in the case where a JPEG decoder is utilized as a test decompressor. Although JPEG algorithm carries out lossy compression, given a test data, the proposed algorithm can search seeds that can be decompressed to another test data preserving the test quality of the given test data, and produce a small set of seeds with high fault coverage. Experimental results show the proposed method can achieve compression ratio comparable with several previous test compression methods without larger hardware overhead.