Deadlock-free routing and component placement for irregular mesh-based networks-on-chip

Author

Schafer, Martin K F ; Hollstein, Thomäs ; Zimmer, Heiko ; Glesner, Manfred

Author_Institution

Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany

fYear

2005

fDate

6-10 Nov. 2005

Firstpage

238

Lastpage

245

Abstract

Routing is one of the most crucial key factors which decides over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-mesh based network-on-chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.

Keywords

circuit layout CAD; integrated circuit layout; logic CAD; network routing; network-on-chip; parallel architectures; 2D-mesh network-on-chip; IP cores; NoC architecture; component placement; deadlock-free routing algorithm; floorplanning method; high density layouts; highly adaptive routing algorithm; parallel computer architecture; routing theories; Algorithm design and analysis; Buildings; Computer architecture; Microelectronics; Network-on-a-chip; Open systems; Routing; System recovery; System-on-a-chip; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on

Print_ISBN

0-7803-9254-X

Type

conf

DOI

10.1109/ICCAD.2005.1560071

Filename

1560071