Novel High Speed MCML 8-Bit by 8-Bit Multiplier

Author

Saha, A. ; Pal, D. ; Chandra, Mahesh ; Goswami, M.K.

Author_Institution

Dr. B.C. Roy Eng. Coll., Durgapur, India

fYear

2011

fDate

24-25 Feb. 2011

Firstpage

1

Lastpage

5

Abstract

Increasing demand for high-speed applications in communication has shaped the need for highly integrated, high speed multiplier. A logic style that is becoming increasingly popular is MOS Current Mode Logic (MCML) due to its distinct advantages over conventional CMOS logic for high-speed applications. In this paper an 8-bit by 8-bit pipelined tree type multiplier designed using MCML, is presented. The architecture is proposed and the operation is explained for high-speed applications supported by simulation results. An optimization method for designing the universal MCML gate for high-speed application is discussed. The optimum throughput for the pipelined tree type multiplier is obtained at 1.31GHz. All simulations are performed on a 0.6μm standard CMOS double metal double poly process, using Cadence Design Tools.

Keywords

circuit optimisation; frequency multipliers; logic circuits; 8-bit × 8-bit pipelined tree type multiplier; MOS current mode logic; cadence design tools; frequency 1.31 GHz; high speed MCML 8-bit × 8-bit multiplier; high-speed application; high-speed applications; optimization method; size 0.6 mum; standard CMOS double metal double poly process; universal MCML gate; Adders; Clocks; Logic gates; Pipeline processing; Registers; Simulation; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices and Communications (ICDeCom), 2011 International Conference on

Conference_Location

Mesra

Print_ISBN

978-1-4244-9189-6

Type

conf

DOI

10.1109/ICDECOM.2011.5738526

Filename

5738526