Simulation of three-dimensional copper-low-k interconnections with different shapes

Interconnect plays a central for nanodevice, very large scale integration (VLSI), and system-on-a-chip (SoC). Investigation of interconnections will significantly benefit both the device fabrication technology and the VLSI SoC design communities (X. Wang et al., 2003). Copper (Cu) has recently become a promising and popular material for the fabrication of interconnections. Unlike aluminum (Al) interconnects, the geometry of fabricated copper interconnects could be changed and deviated from the original structures. We in this work computationally explore the geometry effects on the parasitic elements of interconnect, resistance (R), capacitance (C), and time constant for RC delay (X. Wang et al., 2003 and Y. W. Liu et al., 2000). For a given technology node, the geometry is explored with respect to a minimization of RC time delay. Optimal Cu-low-k interconnect is significant and necessary for SoC era. It also benefits high frequency applications.