Power Aware Shift and Capture ATPG Methodology for Low Power Designs

Power management has emerged as a major design objective, both in functional and test mode, in most of the application domains that employ digital ICs. This paper presents a low power ATPG methodology for managing power both in shift and capture mode. The technique exploits the embedded clock gates and provides a good tradeoff between pattern count and reduction in switching activity without any significant coverage loss. The methodology also presents a novel method of selective scan chain reordering for scan compressed designs to reduce shift switching activity with minimal design flow constraints.