DocumentCode
2803058
Title
A CAL Tool to Aid the Understanding of Logic Synthesis
Author
Tavares, Reginaldo ; Lautenschläger, William ; Reis, Ricardo
Author_Institution
Univ. Fed. do Rio Grande do Sul, Porto Alegre
fYear
2007
fDate
3-4 June 2007
Firstpage
49
Lastpage
50
Abstract
Even if nowadays the logic synthesis process is well defined in an industrial IC Automated Design Flow, it is important that students understand how the logic synthesis works. This paper describes CAL (Computer Aided Learning) tool to help the understanding a logic synthesis flow based on a data structure called ORBDDs. This synthesis flow allows to work over an input logic description and to observe the consequent transformations that occur in each step of the synthesis. The student can change some input parameters to experiment different synthesis solutions.
Keywords
binary decision diagrams; computer aided instruction; logic CAD; computer aided learning; data structure; logic synthesis flow; logic synthesis process; Binary decision diagrams; Boolean functions; Circuit optimization; Circuit synthesis; Data structures; Delay estimation; Logic circuits; Logic design; Logic gates; Multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-7695-2849-X
Type
conf
DOI
10.1109/MSE.2007.5
Filename
4231444
Link To Document