Dual channel and strain for CMOS co-integration in FDSOI device architecture

Author

Royer, C. Le ; Cassé, M. ; Andrieu, F. ; Weber, O. ; Brevard, L. ; Perreau, P. ; Damlencourt, J.F. ; Baudot, S. ; Tabone, C. ; Allain, F. ; Scheiblin, P. ; Rauer, C. ; Hutin, L. ; Figuet, C. ; Aulnette, C. ; Daval, N. ; Nguyen, B.Y. ; Bourdelle, K.K.

Author_Institution

LETI Minatec, CEA, Grenoble, France

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

206

Lastpage

209

Abstract

We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO₂ gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off (I_ON +23% for a given I_OFF =100nA/μm), and thus to obtain similar I_ON for n & pFETs (~650μA/μm at V_DD=1V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted (V_th~+/-0.2V) for high performance (HP) CMOS with a single mid-gap metal gate.

Keywords

CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; field effect transistors; silicon; silicon-on-insulator; CMOS co-integration; FDSOI device architecture; SOI; Si-SiGe; TiN-HfO₂; channel material-strain engineering; dual channel-on-insulator; fully depleted CMOS architecture; gate stack; nFET; short-channel pFET; single mid-gap metal gate; size 1.15 nm to 40 nm; threshold voltages; CMOS integrated circuits; Logic gates; Silicon; Silicon germanium; Threshold voltage; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Conference_Location

Sevilla

ISSN

1930-8876

Print_ISBN

978-1-4244-6658-0

Type

conf

DOI

10.1109/ESSDERC.2010.5618388

Filename

5618388