• DocumentCode
    2807271
  • Title

    Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols

  • Author

    Brown, Geoffrey M. ; Pike, Lee

  • Author_Institution
    Indiana Univ., Bloomington, IN
  • fYear
    2007
  • fDate
    May 30 2007-June 2 2007
  • Firstpage
    171
  • Lastpage
    180
  • Abstract
    This paper demonstrates how to use a satisfiability modulo theories (SMT) solver together with a bounded model checker to prove temporal refinement conditions. The method is demonstrated by refining a specification of the 8N1 protocol, a widely-used protocol for serial data transmission. A nondeterministic finite-state 8N1 specification is refined to an infinite-state implementation in which in- terleavings are constrained by real-time linear inequalities. The refinement proof is via automated induction proofs over infinite-state transitions systems using SMT and model checking, as implemented in SRI International´s Symbolic Analysis Laboratory (SAL).
  • Keywords
    computability; formal specification; formal verification; protocols; temporal logic; 8N1 protocol; SAL; SMT; SRI International Symbolic Analysis Laboratory; finite-state 8N1 specification; model checking; physical-layer protocols; real-time linear inequalities; satisfiability modulo theories; serial data transmission; temporal refinement; Boolean functions; Data communication; Data structures; Formal verification; Hardware; Interleaved codes; Laboratories; Protocols; Safety; Surface-mount technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign, 2007. MEMOCODE 2007. 5th IEEE/ACM International Conference on
  • Conference_Location
    Nice
  • Print_ISBN
    1-4244-1050-9
  • Type

    conf

  • DOI
    10.1109/MEMCOD.2007.371227
  • Filename
    4231794