Experimental analysis of cache memories for interconnect controllers

The effects of cache memories on the performance of interconnect controllers (ICs) are analyzed using trace-driven simulation. Simulation results show that the controllers which interconnect hosts to LANs have a higher hit ratio than those that interconnect network devices to LANs. The impact of cache sizes, set associativity, and line sizes on cache performance is also investigated. A significant observation is that, although increasing the sizes can result in a higher hit ratio, it can also considerably increase traffic to main memory, thereby degrading overall system performance. A method of determining an optimal line size that produces the best overall system performance is therefore needed. A simple analytical model for determining the optimal line size as a function of cache size is presented