A pipelined 650 MHz GaAs 8 K ROM with translation logic

The first commercially available GaAs 8 K ROM has been designed and manufactured using GigaBit Logic´s 3-level metal E/D (enhancement/depletion) MESFET process. The worst-case clock frequency of 650 MHz has been obtained with a power dissipation of 3.5 W. The ROM is organized as 1 K*8 bits, and on-chip translation logic enables the ROM to have an effective 4 K*8 resolution when used as a sine look-up table. The ECL-compatible ROM is packaged in a standard 40-pin package. The pipeline architecture with a delayed internal clock scheme provides fast operation with maximum data valid time at the output of the ROM. The E/D MESFET process, architecture, circuit design, and test results are outlined.<>