PipeRench: a coprocessor for streaming multimedia acceleration

Author

Goldstein, Seth Copen ; Schmit, Herman ; Moe, Matthew ; Budiu, Mihai ; Cadambi, Srihari ; Taylor, R. Reed ; Laufer, Ronald

Author_Institution

Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1999

fDate

1999

Firstpage

28

Lastpage

39

Abstract

Future computing workloads will emphasize an architecture´s ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup

Keywords

coprocessors; multimedia systems; performance evaluation; reconfigurable architectures; reduced instruction set computing; PipeRench; RISC processor; configurations; coprocessor; mixed-width data; multimedia acceleration streaming; performance speedup; reconfigurable fabric architecture; Acceleration; Computer architecture; Coprocessors; Fabrics; Kernel; Optimizing compilers; Reduced instruction set computing; Robustness; Silicon; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architecture, 1999. Proceedings of the 26th International Symposium on

Conference_Location

Atlanta, GA

ISSN

1063-6897

Print_ISBN

0-7695-0170-2

Type

conf

DOI

10.1109/ISCA.1999.765937

Filename

765937