Performance Analysis of Novel 600V Super-Junction Power LDMOS Transistors with Embedded P-Type Round Pillars

A novel 600V super-junction (SJ) power LDMOS device with two different designs of SJ structures has been proposed. The basic SJ structure consists of a number of p-type round pillars buried in an n-type drift layer down to a p-type substrate. Performance characteristics of the device in terms of the trade-off between on-state resistance and breakdown voltage and the sensitivity of the voltage blocking to charge imbalance in the SJ structure were analyzed by means of 3D numerical simulation. The studies show that designing the SJ structure such that it counteracts the substrate-aided depletion effect leads to a significantly reduced sensitivity of the blocking voltage to charge fluctuation at the expense of a slightly degraded performance trade-off.