Modeling of Tunneling Currents for Highly Degraded CMOS Devices

We present a model for tunneling currents in highly degraded CMOS devices. In this field not only well established tunneling mechanisms like Fowler-Nordheim and direct tunneling are important to consider, but also defect-assisted tunneling mechanisms such as elastic and inelastic trap-assisted tunneling and hopping processes between defects. In our work the interaction of several defects in the tunneling process is taken into account. The multi-trap assisted tunneling current is dominant for heavily degraded devices with dielectric thicknesses above approximately 3-4 nm. The filling of traps with carriers leads to space charge and is thus changing device parameters such as threshold-voltage or saturation currents.