A semi-digital cascaded CDR with fast phase acquisition and adaptive resolution control

A semi-digital phase-interpolator based CDR is implemented in 0.18μm CMOS. By employing a cascaded architecture, versatile CDR operation is achieved. The first-stage CDR provides fast acquisition even with large initial frequency difference, followed by the second-stage CDR to further improve the time margin for phase tracking. An adaptive algorithm is used to change the phase resolution of the second stage depending on input frequency offsets, while it optimizes the phase resolution to a best case of 10 bit for small frequency difference. With the first-stage output always available, fast coarse phase acquisition is guaranteed, which is useful for fast system wake up.