DocumentCode
2821293
Title
A new structure for multiprocessor implementation of 2-D denominator-separable filters
Author
Raghuramireddy, D. ; Unbehauen, R.
Author_Institution
Lehrstuhl fuer Allgemeine und Theor. Elektrotechnik, Erlangen-Nurnberg Univ., Germany
fYear
1991
fDate
11-14 Jun 1991
Firstpage
472
Abstract
An efficient multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing is presented based on decomposition techniques and minimizing the throughput delay and maximizing the parallelism. The proposed realization is efficient for the implementation of symmetric fan filters and also suitable for vector processing. The proposed structure possesses a high parallelism and requires a relatively small number of processors; it is amenable to VLSI design with reduced noise properties
Keywords
parallel processing; real-time systems; two-dimensional digital filters; 2D filters; VLSI design; decomposition techniques; denominator-separable filters; digital filters; high parallelism; multiprocessor implementation; real-time processing; symmetric fan filters; throughput delay minimisation; vector processing; Delay effects; Digital filters; Hardware; Image processing; Parallel processing; Polynomials; Radiology; Robot sensing systems; Throughput; Two dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.175999
Filename
175999
Link To Document