DocumentCode
2823947
Title
A frequency synthesizer architecture using frequency difference detection
Author
Albrecht, Steffen ; Sumi, Yasuaki ; Ismail, Mohammed ; Tenhunen, Hannu
Author_Institution
Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol. (KTH), Stockholm, Sweden
Volume
3
fYear
2003
fDate
27-30 Dec. 2003
Firstpage
1155
Abstract
In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
Keywords
counting circuits; frequency synthesizers; voltage-controlled oscillators; clock signal; digital blocks; frequency difference detection; frequency synthesizer architecture; high speed counter; oscillator output frequency; Clocks; Counting circuits; Delay effects; Digital signal processing; Feedback; Frequency conversion; Frequency synthesizers; Signal processing; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562498
Filename
1562498
Link To Document