A 100 MHz single-phase clocked PLA using a novel sense amplifier

Author

Ingelhag, Per ; Svensson, Christer

Author_Institution

LSI Design Center, Linkoping Univ., Sweden

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2983

Abstract

A novel sense amplifier to enhance speed in high-speed array logic is presented. The sense amplifier is simple and can be designed robustly to process variations. The sense amplifier is used in a further development of the single-phase CMOS circuit technique. Two single-phase clocked PLAs have been designed for test purposes. SPICE simulations show that a PLA (with 64 inputs, 256 intermediate AND-functions, 64 outputs, worst-case logical configuration, and with a conservative noise margin) will run faster than 100 MHz in a 2-μm standard CMOS process. One smaller prototype chip has been tested experimentally

Keywords

CMOS integrated circuits; VLSI; amplifiers; circuit analysis computing; logic arrays; 100 MHz; 2 micron; CMOS circuit; SPICE simulations; high-speed array logic; noise margin; prototype chip; sense amplifier; single-phase clocked PLA; single-phase logic; standard CMOS; transistor sizing; worst-case logical configuration; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Clocks; Logic arrays; Noise robustness; Process design; Programmable logic arrays; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176173

Filename

176173