High-Speed, Area-Efficient FPGA-Based Floating-Point Arithmetic Modules

Author

Taher, M. ; Aboulwafa, M. ; Abdelwahab, A. ; Saad, E.M.

Author_Institution

Helwan Univ., Cairo

fYear

2007

fDate

13-15 March 2007

Firstpage

1

Lastpage

8

Abstract

In this paper, single-precision floating-point IEEE-754 standard Adder/Subtractor and Multiplier modules with high speed and area efficient are presented. These modules are designed, simulated, synthesized and optimized by using Mentor Graphics Tools, and they are implemented on an FPGA based system by using the Xilinx Tool (ISE). A comparison between the results of the proposed design and a previously reported one is provided. The effect of normalization unit at the single-precision floating-point multiplier and adder/Subtractor modules on the area, and speed is explained. An FIR filter is implemented on FPGA as an application example.

Keywords

FIR filters; IEEE standards; adders; field programmable gate arrays; floating point arithmetic; multiplying circuits; FIR filter; FPGA; IEEE-754 standard; Xilinx Tool; floating-point adder-subtractor; floating-point arithmetic modules; floating-point multiplier; mentor graphics tools; Automatic control; Clocks; Design optimization; Field programmable gate arrays; Finite impulse response filter; Floating-point arithmetic; Graphics; High level languages; Product design; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2007. NRSC 2007. National

Conference_Location

Cairo

Print_ISBN

977-5031-86-9

Type

conf

DOI

10.1109/NRSC.2007.371368

Filename

4234115