18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Author

Ramanarayanan, R. ; Mathew, Sanu ; Sheikh, Farhana ; SRINIVASAN, SUDARSHAN ; Agarwal, Amit ; Hsu, Steven ; Kaul, Himanshu ; Anders, Mark ; Erraguntla, Vasantha ; Krishnamurthy, Ram

Author_Institution

Circuits Res. Labs., Intel Corp., Hillsboro, OR, USA

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

210

Lastpage

213

Abstract

A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm² with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <;3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range.

Keywords

CMOS integrated circuits; cryptography; microprocessor chips; reconfigurable architectures; CMOS; area reduction; bit rate 18 Gbit/s; frequency 21 MHz to 1.8 GHz; message-digest; microprocessor; multimode secure hashing algorithm accelerator; power 50 mW; reconfigurable hardware accelerator; reconfigurable multimode SHA hashing accelerator; size 45 nm; voltage 320 mV to 1.35 V; Adders; CMOS integrated circuits; Hardware; Power measurement; Registers; Throughput; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2010 Proceedings of the

Conference_Location

Seville

ISSN

1930-8833

Print_ISBN

978-1-4244-6662-7

Type

conf

DOI

10.1109/ESSCIRC.2010.5619892

Filename

5619892