An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS

TAD (Time A/D converter)-composite architecture with 4-shift-clock construction for both fast conversion and increased resolution is presented. An all-digital A/D converter using TAD architecture includes the following: 1) a ring-delay-line (RDL), that is a loop inverter chain, with 16 delay units (DUs), in which delay times are modulated by an A/D conversion voltage V_in for the DU supply voltage; 2) pulse latches; 3) an encoder; and 4) an RDL-frequency counter. The operating principle is to count the number of DUs through which the pulse passes within a sampling time interval T_s with (1/4)LSB-offset for 4-TAD-module by applying a new method named “Clock-Edge-Shift construction (CKES)” to achieve ADC speed-up and resolution-improvement effectively. The 15-bit TAD ADC with 1.2 mm² using a 0.65-μm CMOS achieved both 2.9 mV/LSB at 10 MS/s and 5.7 mV/LSB at 20 MS/s, respectively, by applying the CKES construction with 4-TAD-composite core, resulting in the same level as 0.25-μm digital CMOS performance.