DocumentCode
2824748
Title
Multiple path IEEE floating-point fused multiply-add
Author
Seidel, Peter-Michael
Author_Institution
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Volume
3
fYear
2003
fDate
27-30 Dec. 2003
Firstpage
1359
Abstract
We propose optimizations for the IEEE floating-point fused multiply-add operation by considering multiple exclusive parallel computation paths in the implementation. For the proposed design we can show a significant performance improvement over conventional implementations. Considering a variable latency implementation allows for further reduction of the average latency.
Keywords
adders; floating point arithmetic; multiplying circuits; IEEE; floating-point fused multiply-add operation; multiple exclusive parallel computation paths; variable latency implementation; Added delay; Computer architecture; Computer science; Concurrent computing; Hardware; Optimization methods; Power dissipation; Propagation constant; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562547
Filename
1562547
Link To Document