An algorithm for optimal layouts of CMOS complex logic modules

A new algorithm is presented which finds the optimal layouts of CMOS complex logic modules from the given Boolean logic expressions. The problem of minimizing the layout area of a static CMOS logic module is converted to the problem of determining the covering sets for each sublogic of the given Boolean logic expression and merging all covering sets in all possible ways to find the optimal solution being characterized by the minimum number of dual trails. The problem is known as NP-complete. Typical published algorithms are reviewed and the unsolved issues are discussed. The authors introduce the concepts of 18 canonical symbols, 18 canonical environments, merging cost between each canonical symbol and each canonical environment, dominant canonical symbol sets, complete set of merging sequences, and utilize the concepts to reduce the computing time by avoiding the unnecessary search. The algorithm always guarantees the optimal result