Multiple SimpleScalar processors, with introspection, under SystemC

Currently, multiprocessor embedded systems are the principal vectors of semiconductor industry. Their design is challenging mainly because of the time to market and cost strict constraints. This imposes the evolution of the simulation techniques. New processor simulators have to be powerful, configurable and accurate; they have also to enable easier debugging. To enable overall multiprocessor systems validation, these simulators have to be integrated in hardware/software cosimulation platforms. In this paper we propose an approach for integrating the SimpleScalar simulator in a hardware-software cosimulation platform and the improvement of this simulator by enabling easier micro-architecture debugging. The benefit of this work is that it allows designers to exploit the SimpleScalar simulator capabilities (facilitate configurability, accuracy, performance and portability) for the multiprocessor systems design.