An all digital phase locked loop fault tolerant clock

An implementation of a fault-tolerant clock is presented. The clock is quad redundant, designed according to a structured methodology that is tolerant to faults in any one of its four channels. This was achieved through the use of an all-digital phase-locked-loop (ADPLL) design that maintains synchronization to within 90° between all nonfaulty channels. Experimental results are provided that correlate simulation runs with data obtained from prototype hardware. Methods for further enhancing the design are also presented