A delay model of CML gates valid under high-current effects

Author

Alioto, M. ; Palumbo, G.

Author_Institution

Siena Univ., Italy

Volume

3

fYear

2003

fDate

27-30 Dec. 2003

Firstpage

1556

Abstract

In this paper a delay model of bipolar CML gates which extends that in [M. Alioto, G. Palumbo] for a wide range of bias currents is proposed. In particular, it accounts for high-current effects, i.e. the degradation in the transit time. The model proposed is derived from an approximate circuit analysis and has a simple compact expression as a function of the bias current, that makes it suitable for fast timing analysis or automatic bias current optimization. Simulation of CML circuits with a 20-GHz bipolar process shows that the model has a good accuracy in a wide range of current and loading conditions.

Keywords

SPICE; bipolar logic circuits; circuit simulation; current-mode logic; integrated circuit modelling; logic gates; 20 GHz; CML circuit; automatic bias current optimization; bipolar CML gates; bipolar process; circuit analysis; current-mode logic; delay model; high-current effect; timing analysis; transit time; Circuit analysis; Circuit simulation; Delay effects; Inverters; Logic; Parasitic capacitance; Predictive models; SPICE; Timing; Voltage; Current-Mode logic; Delay model; High-Injection level;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562594

Filename

1562594