VLSI architecture and implementation of a high-speed entropy decoder

An improved variable-length decoder (VLD) architecture which can achieve higher throughput in decoding variable-length codes compared to previously reported VLD architectures is presented. An experimental research prototype VLSI implementation of an entropy decoder which includes the VLD and run-length decoder is also discussed. The chip will be fabricated using a 1-μm double-metal CMOS technology. It is to be used in an experimental prototype high definition television codec with a sample rate of 52 MHz. The chip contains about 46000 transistors in a die size of about 5 mm×5 mm. At 52 MHz, the VLD handles a worst-case input rate of 832 Mb/s and a constant output rate of 416 Mb/s