• DocumentCode
    282969
  • Title

    Modeling of GaAs digital ICs

  • Author

    Merrett, R.P.

  • Author_Institution
    British Telecom Res. Labs., Ipswich, UK
  • fYear
    1988
  • fDate
    32169
  • Firstpage
    42461
  • Lastpage
    42465
  • Abstract
    As custom design approach is needed to achieve the highest performance from a MESFET process. Designers on either an in-house or foundry process, can expect to have access to models which fully describe the circuit elements at their disposal. These models will include device-to-device variations, and the temperature dependence of the various parameters. Designers must, however, expect to derive all the layout dependent capacitances for themselves. There are as yet no parameter extraction software aids for GaAs circuits and automatic placement sacrifices too much circuit performance, but the task of the designer is being eased by the rapidly expanding standard cell libraries. If some performance can be sacrificed, for the sake of reduced design time, then logical analysis can be used. Several foundries are targetting this area of the market and are offering a range of gate arrays which have several speed-power options
  • Keywords
    III-V semiconductors; Schottky gate field effect transistors; circuit analysis computing; digital integrated circuits; field effect integrated circuits; gallium arsenide; semiconductor device models; GaAs; MESFET; circuit elements; custom design; digital ICs; gate arrays; logical analysis; models; speed-power options; standard cell libraries;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Gallium Arsenide, IEE Colloquium on
  • Conference_Location
    London
  • Type

    conf

  • Filename
    208748