A CMOS chip design of binary neural network with delayed synapses

A binary neural network can be easily fabricated because of hardware simplicity. To increase the power of the binary neural network, the authors propose the neural network with delayed synapses for solving optimization problems. They demonstrate a CMOS chip design of the binary neural network with delayed synapses, where the delay inserted into synapse is variable and controllable. Using the 2-μm design rule, 64 neurons can be realized in a chip and every neuron can have 16 different weights and delays of each synapse