Circuit optimization as a tool for the design of 1.0-2.0 GHz CMOS topologies

Author

Pohjonen, Helena ; Andersson, Mikael

Author_Institution

Semicond. Lab., Tech. Res. Centre of Finland, Helsinki, Finland

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2176

Abstract

The authors demonstrate design techniques for high-speed CMOS circuits. Future, integrated telecommunication systems operating within the signal frequency range of 1.0-2.0 GHz will require state-of-the-art semiconductor technologies, system solutions and design tools for the optimization of the most important specifications, like speed-power, temperature stability, noise, and linearities. The authors describe the technological requirements, circuit solutions and the optimization techniques that are suitable for integrating analog-digital RF functions with a scaled CMOS technology

Keywords

CMOS integrated circuits; MMIC; network topology; nonlinear network synthesis; optimisation; 1 to 2 GHz; analog-digital RF functions; circuit optimization; circuit topologies; design techniques; high-speed CMOS circuits; integrated telecommunication systems; linearities; noise; scaled CMOS technology; signal frequency range; speed-power; temperature stability; CMOS technology; Circuit optimization; Circuit stability; Design optimization; Frequency; Integrated circuit technology; Linearity; Semiconductor device noise; Signal design; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176721

Filename

176721