A semicustom clock/timer chip

The authors describe the design and simulation of a gate-array based 7-day programmable clock chip. Modifications to the design to improve testability and suitability for simulation are discussed. The authors detail the various steps in the simulation and design verification. The strategy for generating simulation vectors is also discussed. Due to the high pin count, a 64-lead package was chosen for the chip. The circuitry was implemented in a 5-μm CMOS double-metal gate array design for a prototype. Schematic, layout data, and simulation files were sent to the foundry to fabricate the chips