DocumentCode
2833796
Title
Micro-architecture verification for microprocessors
Author
Bin, Eyal ; Fournier, Laurent
Author_Institution
IBM Labs., Haifa Univ., Israel
fYear
2004
fDate
9-10 Sept. 2004
Firstpage
112
Lastpage
113
Abstract
We present a tool and a methodology for micro-architecture verification of microprocessors. This document serves as an introduction to the invited talk in the special session on micro-architecture verification of microprocessors.
Keywords
computer architecture; formal verification; microprocessor chips; micro-architecture verification; microprocessors; Computer bugs; Conferences; Hardware; Law; Microarchitecture; Microprocessors; Pipelines; Registers; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microprocessor Test and Verification (MTV'04), Fifth International Workshop on
ISSN
1550-4093
Print_ISBN
0-7695-2320-X
Type
conf
DOI
10.1109/MTV.2004.16
Filename
1563081
Link To Document