• DocumentCode
    2833980
  • Title

    Counter reduction techniques for Hamming count

  • Author

    Gleason, Anita ; Jone, Wen-Ben

  • Author_Institution
    Dept. of Comput. Sci., New Mexico Tech., Socorro, NM, USA
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    1980
  • Abstract
    Hardware overhead reduction through counter selection is considered for the Hamming count compaction test. A method to choose the most effective syndrome and input variable counter combination is introduced. Both simulation and theoretical analysis illustrate that the proposed method produces an optimal pairing. Adaptations in the counter selection method are made forming a greedy strategy for choosing multiple counters to combine with the syndrome counter. Complexity of both the single and multiple counter selection algorithms is very reasonable. The method promotes intelligent counter selection to minimize any impact test hardware reduction will have on fault detection
  • Keywords
    VLSI; built-in self test; fault location; integrated circuit testing; integrated logic circuits; logic testing; BIST; Hamming count compaction test; counter selection; counter-reduction techniques; fault detection; greedy strategy; hardware overhead reduction; intelligent counter selection; optimal pairing; syndrome counter; variable counter combination; Analytical models; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computational modeling; Computer science; Counting circuits; Electrical fault detection; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176798
  • Filename
    176798