DocumentCode
2833983
Title
New methods and tools for design of tests memory
Author
Almadi, Mudar ; Moamar, Diaa ; Ryabtsev, Vladimir
Author_Institution
Eur. Univ., Cherkassy, Ukraine
fYear
2011
fDate
9-12 Sept. 2011
Firstpage
319
Lastpage
325
Abstract
For synthesis of algorithms and tests programs of memory diagnosing a system of visualization of algorithms of the tests, containing a control device, a square matrix of memory cells and four heads of record/reading is offered. An example of synthesis by means of the given system of march_PS test. The reduction of labour input of design works is resulted provided at the expense of dynamic visualization of sequence of carried out diagnostic operations.
Keywords
DRAM chips; design for testability; integrated circuit design; integrated circuit testing; matrix algebra; DDR chips; control device; design of test memory method; dynamic visualization; memory cells; Algorithm design and analysis; Complexity theory; Heuristic algorithms; Magnetic heads; Mathematical model; Program processors; Software algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2011 9th East-West
Conference_Location
Sevastopol
Print_ISBN
978-1-4577-1957-8
Type
conf
DOI
10.1109/EWDTS.2011.6116569
Filename
6116569
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